Current techniques for forming plated through holes (i.e., vias) in a printed circuit board substrate include mechanical drilling with a resin fill or laser drilling with a copper fill. Mechanical drilling methods are typically limited to applications with hole diameters of 100 μm or larger because mechanical drill bits tend to break at hole diameters smaller than 100 μm. For applications with hole diameters less than 100 μm, laser drilling technique are preferred. However, laser drilling techniques are typically limited to applications implemented with thin substrates because conventional laser drilling techniques have poor results forming deep holes. For example, the laser drilling process may be prone to various issues with substrate thicknesses greater than approximately 200 μm. One such issue is necking of the hole (i.e., decreasing diameter of the hole near the center of the substrate).
FIG. 1 illustrates conventional laser drilled plated through holes in a thick substrate, in accordance with the prior art. A thick substrate may be a substrate having a thickness that is greater than or equal to 200 μm. As shown in FIG. 1, a printed circuit board 100 may include a layer of substrate 102 (i.e., a dielectric such as FR4) through which one or more vias may be drilled. Although not shown explicitly, most finished PCBs 100 include multiple layers of dielectric material, conductive material (e.g., copper), and/or reinforcement material (e.g., woven glass). As is known in the art, vias may be of different types including, but not limited to, through vias, blind vias, buried vias, and stacked vias.
As shown in FIG. 1, the substrate 102 includes three copper-filled vias 104 laser-drilled through the substrate 102. The necking phenomenon 114 is illustrated as the diameter of the holes decreases towards the center of the substrate. Conventional laser drilling techniques utilize two opposing lasers on either side of the substrate 102, which causes the hole diameter of the vias to reduce to a minimum at approximately the middle of the substrate 102. In addition, copper-filled vias may contain voids 112 due to imperfections of the copper filling process. The voids 112 tend to migrate within the copper material when current passes through the material. If the voids 112 migrate to the surface of the substrate layer, the voids 112 may cause disconnections at the interface of the vias. Thus, there is a need for addressing this issue and/or other issues associated with the prior art.